The present invention relates to electronic device packaging, and more particularly to hermetic packaging of electronic devices. Even more particularly, the present invention relates to multilayer hermetic coating in electronic device packaging.
Integrated semiconductor circuits are critical devices in most electronic systems today. These integrated semiconductor circuits have been broadly used in a variety of fields. Historically, two versions of many integrated semiconductor circuits were designed by manufacturers, one packaged in a non-hermetic plastic package (plastic packaged microelectronics (PEM) device), such as molded epoxy, silicone or phenolic; and another packaged in a hermetic ceramic package. The hermetic ceramic packages were typically used in very sensitive, harsh environment and/or high reliability applications, such as military applications, including weapon systems; space applications, such as for use on Earth space orbit satellites; aerospace applications; ruggedized commercial and medical applications; and transportation applications, such as automotive and avionics applications.
One problem heretofore addressed by hermetic ceramic packages was to prevent the invasion of moisture, ions and other impurities, including oxygen, into critical portions of the package, for example, wire bond sites, and into an integrated semiconductor circuit die. This invasion of impurities can cause oxidation and other erosion of the integrity of the affected structures thereby causing failure of the device. This invasion takes place readily in plastic package devices through cracks or gaps occurring in the molding and in some cases through diffusion through the plastic itself, both of which form paths from an outside environment to the packages contents.
Problematically, in recent years, device manufacturers, for economic reasons, have ceased production of ceramic package devices, thus leaving entities in need of high reliability devices for sensitive applications without a suitable device for their application. Microelectronics are highly susceptible to gases, chemicals and particulates that invade plastic package devices. Pitfalls associated with this sensitivity can include: moisture causing corrosion; chemicals destroying wire bonds, internal circuitry and other pertinent aspects of the device. Further, before a package is added to a device, particulates present in injection molded or otherwise manufactured packages are capable of scratching the surface of the integrated semiconductor circuit die, potentially breaking wire bonds and causing shorts/opens inside the device, and are capable of reacting with or corroding the wire bonds, wires, leads or integrated semiconductor circuit die.
Thus, hermetically sealed packages are required for many applications where contaminants can jeopardize the functional integrity of the device, or where long-term reliability and/or operation in extreme environments are required.
As mentioned above heretofore, the current solution to these issues has been to use ceramic package devices. Ceramic packaging technology provides the hermetic sealing and long-term reliability required by many entities. However, the downfall of these packages has been that they are more expensive than similar plastic packages, tend to weigh more, and require specialized manufacturing equipment to produce. Although, the ceramic package device does effectively address the issue of hermeticity, the ceramic package device frequently provides a level of reliability and ruggedness that exceeds the levels actually required for most applications.
In contrast, the main advantage of plastic package devices is their ability to be mass-produced more cheaply and more easily than other currently available technologies. However, unlike with ceramic package devices, the largest percentages of failures in plastic package devices can be directly or indirectly related to their inherent lack of hermeticity and to the manufacturing techniques employed. Current users of plastic package devices in high-reliability applications are either incurring higher costs for maintenance of inferior products or suffering from a lack of long-term reliability.
A further advantage of plastic package devices is their abilities to operate at higher frequencies due to the lower dielectric constant of plastic, as compared to ceramic. Also, smaller sizes achievable in plastic package devices enables components to be placed closer together, thereby reducing propagation delays. Further, copper leads in plastic package devices have better electrical and thermal conductivity than KOVAR alloy that is used in the leads of ceramic package devices.
Ceramic package devices perform more consistently at high frequency than plastic package devices because moisture in the plastic can vary, changing the dielectric constant of the package and altering the operating speed of the integrated semiconductor circuit die.
Flexibility in low stress plastic formulations is gained at the expense of increased permeability due to the addition of plasticizers.
An alternative to ceramic package devices employs “wafer-level” coating of the integrated semiconductor circuit die itself, which adds yet more complexity to the manufacturing process, and brings with it engineering challenges as well. The die level application of the coating increases the hermeticity of the integrated semiconductor circuit die as well as the structural reliability of the device at a lower cost and in a manner that can be integrated into current production facilities. Unfortunately, this process must be performed as a fabrication step, before the integrated semiconductor circuit die is cut from the wafer, and thus requires altering “fab” processes. Problematically, once the integrated semiconductor circuit die is cut from the water, edges of the integrated semiconductor circuit die remain exposed and susceptible to contaminants. Furthermore, bonding pads on the surface of the integrated semiconductor circuit die must be exposed (for wire bonding for example) and thus create a further point of susceptibility to contamination. And, disadvantageously, this approach does nothing to protect the wires or wire bonds, a common point of contamination-caused failure. U.S. Pat. No. 5,780,163, issued to Camilletti et al., provides an example of “water-level” coating.
Hermetic coatings have also been applied to the integrated semiconductor circuit die and wire bonds after the die is attached to a die attach substrate and the wires are wire bonded to the integrated semi-conductor circuit die and leads. These hermetic coatings use plasma chemical vapor deposition of silicon nitride to prevent moisture from contaminating the device. This process can also be done to deposit diamond like carbon, silicon oxide and other insulating materials. One example of this type of hermetic coating is shown in U.S. Pat. No. 5,096,851, issued to Yamazaki et al.
Single layer PARYLENE coatings (para-xylylene) have been applied to the integrated semiconductor circuit die and wire bonds prior to packaging for the purpose of allowing for distortion of the wire bonds without short circuiting and reducing the requirements for high tolerances associated with relatively short length wires. U.S. Pat. No. 5,824,568, issued to Zechmans describes single layer PARYLENE coatings.
Bi-layer and tri-layer coating technologies have also been developed to provide moisture and oxygen barriers using any of parylene/BCB (cyclotene®)/SiO2, parylene/A1203, and parylene/SiO2. In these approaches, a PARYLENE layer is first applied, and then one or more subsequent ceramic layers are applied.